Design of reconfigurable coprocessor for communication systems

This paper proposes a reconfigurable coprocessor for communication systems, which can support high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc., and it can be used for next generation communication platforms to satisfy high speed operations. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 μm standard cell library. The gate count is about 35,000 and the critical path is 3.84 ns with the 0.18 μm technology. The proposed coprocessor shows performance improvements compared with existing DSP chips for communication algorithms.