Impact of technology scaling on bridging fault detections in sequential and combinational CMOS circuits

It is well known that classical fault models (stuck-at, stuck-open, stuck-on) cover only partially the spectrum of failures in today´s integrated circuits (IC). Some realistic failures occurring in logic circuits have to be considered at the physical level and include its electrical behavior. Among these failures, gate-oxide short, floating gate and bridging fault types may produce intermediate voltages with difficult interpretations at logic level. This work investigates the influence of a bridging fault (BF) between two interconnection lines on the logic margin and logic swing of an IC and the sensitivity of digital ICs realized on four different technologies (0.25 μm, 0.35 μm, 0.5 pm. 1.5 μm) to bridging faults. Several circuits, including D flip-flops and ISCAS benchmark circuits, were analyzed to find out the impact of technology scaling on BF defects detection. In this work we show that the sensitivity of an IC to BF is increased with technology scaling. The testing methodology was based on the use of voltage, temperature and frequency as parameters, which influence on the behavior of an IC with BF