IDDQ profiles: a technique to reduce test escape and yield loss during IDDQ testing

We describe a new framework that we call the I_DDQ profile technique to minimize test escape (TE) and yield loss (YL) during I_DDQ testing. The proposed framework defines the concept of the I_DDQ profile of a fault P_k, that provides a link between the faults severity and different test vectors. The framework provides various strategies to select a subset of the I _DDQ profiles of modeled faults and provides a mechanism to compute test escape and/or yield loss. The framework is illustrated using an SRAM as a case study. The results demonstrate various trade-offs that can be explored using the framework, and that lower test escape (for zero yield loss) and lower yield loss (for zero test escape) can be obtained compared to known techniques