Title :
Testing of deep-submicron battery-operated circuits using new fast current monitoring scheme
Author :
Margala, Martin ; Pecuh, Ivan
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
This paper presents an on-chip scheme for the testing of deep-submicron low-voltage circuits using low-voltage quiescent current-Iddq and transient current-Iddt monitoring. The scheme utilizes two types of current monitors, the Single-Resistor Monitor (SRCM) and the Dual-Resistor Monitor (DRCM). The current monitors are designed for low-voltage digital and analog CMOS circuits (1.5 V). The monitors are capable of detecting open and short faults at significantly higher speeds than previously reported in the literature (up to 100 MHz operation). The effect of this scheme on the circuit-under-test performance is negligible. The monitors have been implemented in 0.5 μm and 0.35 μm CMOS technologies, and experimentally verified on several digital and mixed-signal circuits
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; condition monitoring; electric current measurement; integrated circuit testing; low-power electronics; mixed analogue-digital integrated circuits; 0.35 micron; 0.5 micron; 1.5 V; 100 MHz; LV analog CMOS circuits; LV digital CMOS circuits; LV quiescent current-Iddq monitoring; LV transient current-Iddt monitoring; current monitors; deep-submicron LV circuits; deep-submicron battery-operated circuits; dual-resistor monitor; fast current monitoring scheme; low-voltage circuits; mixed-signal circuits; onchip scheme; open faults; short faults; single-resistor monitor; CMOS digital integrated circuits; Capacitors; Circuit faults; Circuit testing; Computerized monitoring; Diodes; Mirrors; Resistors; Virtual colonoscopy; Voltage;
Conference_Titel :
Defect Based Testing, 2000. Proceedings. 2000 IEEE International Workshop on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0637-2
DOI :
10.1109/DBT.2000.843692
