Low Power High Performance Digitally Assisted Pipelined ADC

Pipeline analog to digital converters are subject to different errors caused by analog circuit imperfections which limit their accuracy. Much work has been done in recent years to compensate for these errors in the digital domain. However, none of them has addressed all possible errors. Only few of them compensate for higher order nonlinearity in pipeline interstage gain which can be the limiting factor for high resolutions (i.e.14-bit and over). This paper presents the design of a 14-bit 50 Msps pipeline ADC using a comprehensive calibration engine. Linear, nonlinear and memory errors in the residue stage as well as the capacitor mismatch in the multibit internal DAC are all compensated for in a digital calibration unit. The design also incorporates a novel approach for estimating higher order nonlinearities. Circuit implementation of the ADC and trade-offs in the system and circuit level design are discussed in detail. The 14-bit 50 Msps pipeline ADC is implemented in 0.25 um technology and consumes 170 mw from a 2.5 V supply. The power consumption of the digital calibration circuit is estimated to be 30 mw using a 1 V supply.