High Speed Ultra Low Voltage CMOS inverter

Author

Berg, Yngvar ; Mirmotahari, Omid ; Lomsdalen, Johannes Goplen ; Aunet, Snorre

Author_Institution

Dept. of Inf., Univ. of Oslo, Oslo

fYear

2008

fDate

7-9 April 2008

Firstpage

122

Lastpage

127

Abstract

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.

Keywords

CMOS integrated circuits; high-speed integrated circuits; invertors; low-power electronics; CMOS process; Spectre simulator; ULV; effective threshold voltage; high speed ultra low voltage CMOS inverter; offsets voltages; semi-floating-gate nodes; size 90 nm; ultra low voltage logic dates; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Circuit synthesis; Energy consumption; Inverters; Leakage current; Low voltage; Threshold voltage; CMOS; Low voltage; high speed; inverter; semi floating-gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual

Conference_Location

Montpellier

Print_ISBN

978-0-7695-3291-2

Electronic_ISBN

978-0-7695-3170-0

Type

conf

DOI

10.1109/ISVLSI.2008.23

Filename

4556781