DocumentCode :
2012195
Title :
A design-for-reliability approach based on grading library cells for aging effects
Author :
Arasu, S. ; Nourani, M. ; Carulli, John M. ; Butler, Kenneth M. ; Reddy, Veerababu
Author_Institution :
Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA
fYear :
2013
fDate :
6-13 Sept. 2013
Firstpage :
1
Lastpage :
7
Abstract :
A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.
Keywords :
ageing; integrated circuit reliability; logic design; logic gates; aging effects; cell gate reliability characterization; design-for-reliability approach; fixed pessimistic end-of-life method; grading library cells; library cell grading information; parametric degradation; Abstracts; Libraries; Logic gates; Reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2013 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2013.6651923
Filename :
6651923
Link To Document :
بازگشت