A Novel System on Chip (SoC) Test Solution

Author

Higgins, Michael ; MacNamee, Ciaran ; Mullane, Brendan

Author_Institution

Dept. of Electron. & Comput. Eng., Limerick Univ., Limerick

fYear

2008

fDate

7-9 April 2008

Firstpage

145

Lastpage

150

Abstract

A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a test access mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.

Keywords

IEEE standards; integrated circuit testing; system-on-chip; IEEE 1149.1 state machine; IEEE 1500 standard; IEEE P1687 standard; SoC testing; system on chip; test access mechanism; test controller architecture; Automatic control; Circuit testing; Control systems; Instruments; Integrated circuit interconnections; Integrated circuit testing; Silicon; System buses; System testing; System-on-a-chip; IEEE 1500; IEEE P1687; System Bus Reuse; TAM; Test Controller;

fLanguage

English

Publisher

ieee

Conference_Titel

Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual

Conference_Location

Montpellier

Print_ISBN

978-0-7695-3291-2

Electronic_ISBN

978-0-7695-3170-0

Type

conf

DOI

10.1109/ISVLSI.2008.36

Filename

4556785

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2012225