An efficient reformulation based VLSI architecture for adaptive Viterbi decoding in wireless applications

New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. The authors present a reformulation based VLSI architecture for threshold selection for adaptive Viterbi decoding in wireless applications. Through reformulation of the adaptive Viterbi algorithm, the compare operation for threshold selection in the add compare select (ACS) unit is simplified from variable based to constant based and the width of the path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and look up table (LUT) technologies. The paper describes the reformulation technique, its VLSI architecture for adaptive Viterbi decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric memory unit (PMU).