Title :
Diagnosis and Layout Aware (DLA) scan chain stitching
Author :
Jing Ye ; Yu Huang ; Yu Hu ; Wu-Tung Cheng ; Ruifeng Guo ; Liyang Lai ; Ting-Pu Tai ; Xiaowei Li ; Weipin Changchien ; Daw-Ming Lee ; Ji-Jan Chen ; Eruvathi, Sandeep C. ; Kumara, Kartik K. ; Liu, Cong ; Sam Pan
Author_Institution :
State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
Abstract :
Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS´89/ITC´99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
Keywords :
automatic test pattern generation; benchmark testing; design for testability; elemental semiconductors; fault diagnosis; integrated circuit testing; silicon; DLA scan chain stitching method; ISCAS´89 benchmark circuits; ITC´99 benchmark circuits; Si; chip performance; diagnosis and layout aware; diagnostic resolution; embedded scan compaction; sensitive scan cells; size 20 nm; stitching scan cells; test power dissipation; transition fault coverage; Ant colony optimization; Automatic test pattern generation; Circuit faults; Computer architecture; Layout; Microprocessors; Routing;
Conference_Titel :
Test Conference (ITC), 2013 IEEE International
Conference_Location :
Anaheim, CA
DOI :
10.1109/TEST.2013.6651929