Title :
High-performance adaptive GPS attitude determination VLSI architecture
Author :
Stefatos, E.F. ; Arslan, T.
Author_Institution :
Sch. of Eng. & Electron., Edinburgh Univ., UK
Abstract :
The paper presents an adaptive VLSI hardware architecture for an attitude determination system (ADS), which is based on Global Positioning System (GPS) measurements. The system composes the digital core of a GPS receiver, which manipulates the input data in order to resolve the attitude of a vehicle. The adaptation of this architecture is achieved by using a fine-grained parallel genetic algorithm (PGA) that is employed to compute more efficiently the attitude determination algorithm in terms of speed performance. The PGA consists of 64 processing elements (PEs), which are connected in the formation of an 8/spl times/8 array. Moreover, the hardware block that computes the fitness function of the PGA employs coordinate rotation digital computer (CORDIC) algorithms in order to increase the throughput rate of the ADS further.
Keywords :
Global Positioning System; VLSI; adaptive signal processing; attitude measurement; genetic algorithms; integrated circuit design; parallel algorithms; CORDIC algorithms; GPS receiver; Global Positioning System; VLSI architecture; adaptive GPS attitude determination system; adaptive VLSI hardware architecture; coordinate rotation digital computer algorithms; digital core; fitness function; hardware design; parallel genetic algorithm; processing elements; throughput rate; Computer architecture; Concurrent computing; Electronics packaging; Genetic algorithms; Global Positioning System; Hardware; Position measurement; Throughput; Vehicles; Very large scale integration;
Conference_Titel :
Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on
Conference_Location :
Austin, TX, USA
Print_ISBN :
0-7803-8504-7
DOI :
10.1109/SIPS.2004.1363055
