Design rule check on the clock gating logic for testability and beyond

Author

Kun-Han Tsai ; Shuo Sheng

Author_Institution

Mentor Graphics, Silicon Test Solutions, Wilsonville, OR, USA

fYear

2013

fDate

6-13 Sept. 2013

Firstpage

1

Lastpage

8

Abstract

The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.

Keywords

automatic test pattern generation; design for testability; logic circuits; logic design; logic testing; ATPG method; DRC algorithm; automatic test pattern generation; clock gating logic; clock gating structures; design rule check algorithm; process variations; race condition; silicon failure; test coverage lost minimization; testability; timing uncertainty; voltage droop; Automatic test pattern generation; Clocks; Debugging; Latches; Logic gates; Timing; Automated Test Pattern Generation (ATPG); Design Rule Check (DRC); Design-for-Test (DFT); Event-Driven Logic Simulation; Testability; Timing Validation; Timing Variation;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Type

conf

DOI

10.1109/TEST.2013.6651930

Filename

6651930