Hardware design of image information processor based on ADSP-TS201 DSPs

This paper studies on the hardware design and implementation of a universal multi-DSP and FPGA image information processor in accordance with the PCI-E and CPCI specifications. The image information processor features two clusters of total four ADSP-TS201 TigerSHARC DSPs from ADI as the kernel processing unit, reconfigurable framework implemented by two Xilinx Virtex-5 FXT FPGA chips. Taking full advantage of the high performance, unprecedented I/O bandwidth of TigerSHARC DSP and Virtex-5 FXT FPGA, the processor can easily meet the huge image processing and computing work. The hardware design of high speed linkport interconnection between TS201 DSPs and FPGA chips is described.