Title :
Evaluation of the BSIM6 compact MOSFET model´s scalability in 40nm CMOS technology
Author :
Chalkiadaki, M.-A. ; Mangla, A. ; Enz, C.C. ; Chauhan, Y.S. ; Karim, M.A. ; Venugopalan, S. ; Niknejad, A. ; Hu, C.
Author_Institution :
Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
Abstract :
The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based compact model BSIM6 has been developed. In this article, as a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used. The model is compared against a state-of-the-art 40nm CMOS technology. The results attest the model´s scalability under all bias conditions, proving its reliability for nowadays complex IC designs.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; BSIM6; CMOS technology; IC designs; MOS transistor; aggressive downscaling; compact MOSFET; CMOS integrated circuits; CMOS technology; Integrated circuit modeling; MOSFET circuits; MOSFETs; Predictive models; Semiconductor device modeling;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-1707-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2012.6343331
