A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction

This paper presents a new buffer sizing methodology for clock meshes. Mesh buffers are usually sized according to the load present in its vicinity. This approach targets at equalizing mesh buffer propagation delays and hence minimizing clock skew. We show that this approach is not well suited when clock signal presents different arrival times at the mesh buffer inputs (i.e. global clock network skew is not zero). Two mesh buffer sizing algorithms are proposed. The first one sizes clock mesh buffers according to the estimated clock arrival time at each mesh buffer input while the second method considers the probability of the clock signal arrival time be within a certain interval. Our experiments show that clock skew can be improved in 8.5% and clock mesh power consumption reduced in 20%.