Efficient hardware realization of IRA code decoders

Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of low-density parity-check (LDPC) codes and can even outperform the recently introduced turbo-codes of current communication standards. Implementation complexities like area and achievable throughput of these channel coding schemes have a major impact on the decisions of standardization committees. In this paper, we investigate implementation issues of IRA codes and analyze the strong interdependency of code performance and architectural dependencies, like throughput and area. We present an architecture template which is capable of decoding hardware optimized IRA codes which can outperform turbo-codes. We demonstrate this new approach through instances synthesized in a 0.13 μm technology.