A Network Based Functional Verification Method of IEEE 1394a PHY Core

The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the main tasks in the design flow, aiming to certify the system functionality has been accomplished accordingly to the specification. A simulation based technique known as functional verification has been followed widely. In recent years, articles in functional verification have been presented, focusing on specific design verification and on methods to improve and accelerate coverage reaching. The majority of the papers are aimed to processors verification, while communication network designs were not such commonly reported. In the present paper, we present a novel and efficient network based functional verification method applied to an IEEE 1394a PHY core. The method presented reduces verification time, by automation in generating input signals from network, and parallelism in multi designs under verification of different physical and logical roles in network topology. The method can also be used in the functional verification of similar communication network designs.