Increasing the performance of Finite-Set Model Predictive Control by oversampling

This paper presents an FPGA-based implementation of Finite-Set Model Predictive Control (FS-MPC) which makes use of oversampling in order to achieve a better control result: In general the maximum IGBT switching frequency is limited to half the sampling frequency for all FS-MPC methods. In simulations and practical implementations, however, it can be seen that the real switching frequency is far lower than its theoretical maximum. Especially for lower power applications where a good quality of the output variables is important, FS-MPC shows very high ripples compared to modulation-based approaches. The main reason for this is that conventional control systems have sampling cycle times which are normally in the range of 20 μs to 200 μs. By using FPGAs, the sampling frequency of the control system can be significantly increased, as the control is completely implemented in hardware. Experimental results for current control of a single-phase resistive-inductive load and for output voltage control of a single-phase Uninterruptible Power Supply (UPS) with a Neutral Point Clamped (NPC) inverter demonstrate the power of the proposed method. A voltage balancing algorithm for the DC link capacitors of the two inverter legs is included in the cost function as well as certain weighting factors to limit the IGBT switching frequency.