Title :
Node prefetch prediction in dataflow graphs
Author :
Petersen, Newton G. ; Wojcik, Martin R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
Abstract :
Dataflow languages provide a high-level description that can expose inherent parallelism in many applications. This high level description can be applied to automatically create efficient code and schedules based on patterns in the dataflow graphs and knowledge of the target architecture. When targeting a dataflow graph to custom hardware, it is sometimes advantageous to share nodes with similar functionality to save silicon. Any state information associated with the caller of the shared node must be stored and subsequently loaded upon firing. If prediction logic can predict which caller of a shared node is next, the associated state information can be prefetched while other nodes of the graph are executing. While some applications can be entirely scheduled at compile time, many multi- channel measurement and control applications require some degree of dynamic scheduling. This paper´s key contribution is a lightweight call prediction unit with 100% prediction accuracy given a runtime-determined periodic calling schedule. While applications are varied, we show a 33% speedup in a filtering application possible in wireless ad hoc networks.
Keywords :
data flow graphs; parallel architectures; pipeline processing; processor scheduling; storage management; branch prediction; caller prediction; dynamic scheduling; dynamically scheduled dataflow graphs; high level description languages; inherent parallelism; lightweight call prediction unit; multichannel control systems; multichannel measurement systems; node prefetch prediction unit; parallel processing system; pipelined processors; prediction accuracy; prefetched state information; runtime-determined periodic calling schedule; shared nodes; wireless ad hoc network filtering; Computational modeling; Dynamic scheduling; Hardware; Parallel processing; Predictive models; Prefetching; Processor scheduling; Runtime; Silicon; Switches;
Conference_Titel :
Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on
Print_ISBN :
0-7803-8504-7
DOI :
10.1109/SIPS.2004.1363068