DocumentCode
2012628
Title
A bootstrapped NMOS charge recovery logic
Author
Yoo, Seung-Moon ; Kang, Sung-Mo
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fYear
1998
fDate
19-21 Feb 1998
Firstpage
30
Lastpage
33
Abstract
This paper describes a new bootstrapped NMOS charge recovery logic (BNCRL) which realizes low energy computation. Power comparison with a state-of-the-art adiabatic charge recovery circuit is shown for an inverter chain and an 8-bit adder. The new logic circuits exhibit full rail-to-rail logic swing, less dependency of energy consumption on output load capacitance variations, and significant energy saving. Benchmark circuits were designed for comparison using 0.6-μm CMOS technology
Keywords
MOS logic circuits; adders; bootstrap circuits; capacitance; logic gates; 8 bit; adder; bootstrapped NMOS charge recovery logic; energy computation; energy consumption; energy saving; inverter chain; output load capacitance; rail-to-rail logic swing; Adders; CMOS logic circuits; CMOS technology; Capacitance; Circuits; Diodes; Energy consumption; Inverters; Logic; Logic circuits; MOS devices; MOSFETs; Rail to rail outputs; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location
Lafayette, LA
ISSN
1066-1395
Print_ISBN
0-8186-8409-7
Type
conf
DOI
10.1109/GLSV.1998.665195
Filename
665195
Link To Document