SeReCon: A Secure Dynamic Partial Reconfiguration Controller

As reconfigurable computing systems become more popular, concerns arise about their security and integrity. Runtime access to the configuration memory of dynamic partially reconfigurable FPGA devices offers new design possibilities, but also introduces security threats. This paper discusses various security threats present in such systems. The paper proposes a secure reconfiguration controller (SeReCon) which provides secure runtime management of designs downloaded to the DPR FPGA system and protects the design IP. SeReCon requires minor modification to the FPGA fabric. A prototype implementation of SeReCon is evaluated.