Title :
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs
Author :
Boden, Maik ; Fiebig, Thomas ; Reiband, Markus ; Reichel, Peter ; Rulke, S.
Author_Institution :
Fraunhofer IIS/EAS, Dresden
Abstract :
This paper presents GePaRD, a novel approach to High-Level Synthesis of self-adaptive systems based on Partially Reconfigurable (PR) FPGAs. GePaRD combines Temporal Modularization and Temporal Placement in order to reduce the reconfiguration overhead at runtime by extracting Temporal Reusable Modules. We introduce the basics of High-Level PR design as well as the GePaRD design steps (transformations) and GePaRD descriptions (models). Moreover, we describe our approach to Temporal Modularization using Greedy Clique Partitioning and Temporal Placement using Simulated Annealing.
Keywords :
field programmable gate arrays; high level synthesis; logic design; GePaRD; high-level generation flow; high-level synthesis; partially reconfigurable FPGA; partially reconfigurable designs; self-adaptive systems; temporal modularization; temporal placement; temporal reusable modules; Adaptive systems; Computer Society; Computer architecture; Field programmable gate arrays; High level synthesis; Reconfigurable architectures; Resource management; Runtime; Simulated annealing; Switches; FPGA Design; High Level Synthesis; Partial Dynamic Reconfiguration; Temporal Modularization; Temporal Placement;
Conference_Titel :
Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Conference_Location :
Montpellier
Print_ISBN :
978-0-7695-3291-2
Electronic_ISBN :
978-0-7695-3170-0
DOI :
10.1109/ISVLSI.2008.21