DocumentCode
2012715
Title
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties
Author
Lee, J. ; Vijaykrishnan, N. ; Irwin, M.J. ; Radhakrishnan, R.
Author_Institution
Embedded & Mobile Comput. Design Center, Pennsylvania State Univ., University Park, PA, USA
fYear
2004
fDate
13-15 Oct. 2004
Firstpage
361
Lastpage
366
Abstract
In this paper, a novel architecture for 2D IDCT is proposed, based on the sparseness property of 2D DCT coefficient matrix and the even and odd symmetry property of the basis vectors of the 1D DCT transform. The proposed architecture performs 2D IDCT directly on the 2D DCT coefficient matrix to avoid timing and area overheads of the transposition. We derive a recursion equation from the definition of the 2D IDCT algorithm and use it to design an efficient 2D IDCT architecture. The proposed architecture consists of highly regular, parallel and pipelined elements which are suitable for VLSI implementation. It is shown that the proposed architecture can achieve a high throughput rate and a low hardware complexity, when compared with other DCT-based IDCT architectures. Another important aspect is that the proposed architecture can provide an efficient way to control the trade-off between visual quality of the reconstructed image and computational complexity.
Keywords
VLSI; computational complexity; discrete cosine transforms; image coding; image reconstruction; pipeline processing; sparse matrices; 2D IDCT; VLSI implementation; coefficient matrix; computational complexity; hardware complexity; highly regular pipelined elements; inverse discrete cosine transform architecture; parallel pipelined elements; reconstructed image; recursion equation; sparseness; symmetry properties; throughput rate; visual quality; Algorithm design and analysis; Computer architecture; Discrete cosine transforms; Discrete transforms; Equations; Hardware; Image reconstruction; Throughput; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on
Print_ISBN
0-7803-8504-7
Type
conf
DOI
10.1109/SIPS.2004.1363077
Filename
1363077
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