Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme

In this paper a fast and accurate upper-bound power consumption estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware implementation as a single alternative, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound the latency range for different hardware implementations. The presented estimation tool estimates the power consumption for these two hardware alternatives. The computational cost of the presented estimation tool depends linearly on the design complexity as no simulation processes are performed, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate. Overall power consumption estimations are within plusmn4% of the actual power consumed with an average of 1% error. However, Logic Elements (LEs) and clock power estimates are accurate with an average error of 8.25% and 6.25%, respectively.