Title :
A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement
Author :
Li, Qi ; Wang, Bo ; Kim, Tony T.
Author_Institution :
IC Design Centre of Excellence, Nanyang Technol. Univ., Singapore, Singapore
Abstract :
A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V.
Keywords :
CMOS memory circuits; SRAM chips; circuit stability; integrated circuit testing; CMOS technology; SRAM; cell stability improvement; energy 5.61 pJ; half-select-free write operation; local write-back; read bitline voltage swing; sensing timing window; single-ended equalized bitline scheme; size 65 nm; test chip; voltage 0.24 V; voltage 0.3 V; Computer architecture; Delay; Microprocessors; Random access memory; Sensors; Voltage control;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-1707-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2012.6343368
