DocumentCode
2013069
Title
An advanced statistical compact model strategy for SRAM simulation at reduced VDD
Author
Asenov, P. ; Reid, D. ; Roy, S. ; Millar, C. ; Asenov, A.
Author_Institution
Device Modelling Group, Univ. of Glasgow, Glasgow, UK
fYear
2012
fDate
17-21 Sept. 2012
Firstpage
205
Lastpage
208
Abstract
Accurate statistical compact model extraction and circuit simulation are key issues in contemporary SRAM design. The high statistical variability of the small SRAM cell transistors in combination with high density leads to yield problems determined by 5-6σ deviations from the mean. The compact modeling approach presented in this paper utilizes a firm understanding of the physical phenomenon underlying device variability. Its illustration is based on comprehensive `atomistic´ 3D device simulations. Extracted statistical models are then utilized in SRAM SNM simulation, and benchmarked against Gaussian VT based simulation. The results show that aside from the increasing error in the yield estimate with the reduction of the supply voltage VDD, Gaussian VT simulations also fail to capture the decorrelation between nominal SNM and SNM.
Keywords
Gaussian processes; SRAM chips; semiconductor device models; statistical analysis; Gaussian VT based simulation; SRAM SNM simulation; SRAM cell transistor; SRAM design; atomistic 3D device simulation; circuit simulation; statistical compact model extraction; statistical variability; Correlation; Integrated circuit modeling; Predictive models; Random access memory; Semiconductor device modeling; Threshold voltage; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European
Conference_Location
Bordeaux
ISSN
1930-8876
Print_ISBN
978-1-4673-1707-8
Electronic_ISBN
1930-8876
Type
conf
DOI
10.1109/ESSDERC.2012.6343369
Filename
6343369
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