Title :
A VLSI neuroprocessor for real-time image flow computing
Author :
Fang, Wai-Chi ; Sheu, Bing J. ; Lee, Ji-Chien
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A locally connected multi-layer stochastic neural network and its associated VLSI array neuroprocessors have been developed for high-performance image flow computing systems. An extendable VLSI neural chip has been designed with a silicon area of 4.6×6.8 mm2 in a MOSIS 2 μm scalable CMOS process. The mixed analog-digital design techniques are utilized to achieve compact and programmable synapses with gain-adjustable neurons and winner-take-all cells for massively parallel neural computation. Hardware annealing through the control of the neurons´ gain helps to efficiently search the optimal solutions. Computing of image flow using one 2 μm 72-neuron neural chip can be accelerated by a factor of 187 more than a Sun-4/260 workstation. Real-time image flow processing on industrial images is practical using an extended array of VLSI neural chips. Actual examples on moving trucks are presented
Keywords :
CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; neural nets; 2 micron; MOSIS scalable CMOS process; VLSI neuroprocessor; extendable VLSI neural chip; gain-adjustable neurons; hardware annealing; industrial images; massively parallel neural computation; mixed analog-digital design techniques; moving trucks; real-time image flow computing; winner-take-all cells; Analog-digital conversion; CMOS process; Computer networks; Multi-layer neural network; Neural network hardware; Neural networks; Neurons; Silicon; Stochastic systems; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-0003-3
DOI :
10.1109/ICASSP.1991.150887