Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis

On chip signal crosstalk is a function of switching activity pattern, coupling parasitics, and signal timing. We propose a simulated annealing (SA) based high-level synthesis algorithm for crosstalk activity minimization for a given data environment. We target bus-based architectures as the bus-lines have well-defined neighborhood (aggressors). Our objective is to minimize worst-case crosstalk patterns by exploring synthesis solutions with correlations that do not result in such worst-case patterns. Besides synthesis moves, we also incorporate bus re-ordering and data transfer invert encoding. Experimental results for design under resource as well as latency constraints are promising. For a set of three DSP benchmarks we reduce up to 75% of buses that require no shielding lines.