Efficient Realization of Strongly Indicating Function Blocks

This paper presents a technique for efficient gate-level realization of strongly indicating function blocks. For the function block implementing the desired logic, the input state space explodes as it expands exponentially for even a gradual increase in the number of inputs. In this context, a novel design-methodology for realizing non-regenerative logic as a function block, under the discipline of quasi-delay insensitivity with four-phase handshaking and dual-rail encoding, which adheres to the strongly indicating timing regime has been discussed. Approximately 3 times reduction in transistor cost has been achieved by the proposed method in comparison with a recent work, based on analysis with benchmarks and widely used digital circuit functionality; in particular cases the savings are remarkable.