DocumentCode :
2013194
Title :
A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase
Author :
Kume, H. ; Tanaka, T. ; Adachi, T. ; Miyamoto, N. ; Saeki, S. ; Ohji, Y. ; Ushiyama, M. ; Kobayashi, T. ; Nishida, T. ; Kawamoto, Y. ; Seki, K.
Author_Institution :
Hitachi Device Engineering Co., Japan
fYear :
1991
fDate :
28-30 May 1991
Firstpage :
77
Lastpage :
78
Keywords :
CMOS process; CMOS technology; Circuits; Flash memory; Flash memory cells; Hot carrier injection; Laboratories; Split gate flash memory cells; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on
Conference_Location :
Oiso, Japan
Type :
conf
DOI :
10.1109/VLSIT.1991.705998
Filename :
705998
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2013194
