Title :
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip
Author :
Chowdhury, Masud H. ; Gjanci, Juliana ; Khaled, Pervez
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Chicago, Chicago, IL
Abstract :
Conventional power gating techniques for minimizing leakage currents introduce ground bounce noise during power mode transition. Here an analysis of ground bounce due to power mode transition in power gating structures is presented. An innovative power gating approach is proposed, which in addition to targeting maximum reduction of major leakage currents will provide a way to control ground bounce during power mode transition. The proposed power gating technique will have an additional intermediate HOLD mode along with conventional CUTOFF and RUN modes. Its stepwise turning on feature will provide higher reduction of the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.
Keywords :
circuit noise; leakage currents; system-on-chip; ground bounce noise; leakage currents; peak current; power distribution network; power gating scheme; power gating structures; power mode transition; system-on-a-chip; voltage glitches; Circuit noise; Control systems; Integrated circuit noise; Leakage current; Packaging; Power system reliability; Rails; Resonance; System-on-a-chip; Voltage; Power gating; ground bounce; leakage; sleep transistor; substrate noise; system-on-a-chip;
Conference_Titel :
Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Conference_Location :
Montpellier
Print_ISBN :
978-0-7695-3291-2
Electronic_ISBN :
978-0-7695-3170-0
DOI :
10.1109/ISVLSI.2008.85
