Title :
A silicon photomultiplier with >30% detection efficiency from 450–750nm and 11.6μm pitch NMOS-only pixel with 21.6% fill factor in 130nm CMOS
Author :
Webster, Eric A G ; Walker, Richard J. ; Henderson, Robert K. ; Grant, Lindsay A.
Author_Institution :
Inst. for Integrated Micro & Nano Syst., Univ. of Edinburgh, Edinburgh, UK
Abstract :
A 16×16 Silicon Photomultiplier (SiPM) is reported in a 130nm CMOS imaging technology with a photon detection probability of >;30% from 450-750nm. The SiPM demonstrates a 21.6% fill factor with an 11.6μm pitch and 8μm diameter SinglePhoton Avalanche Diodes (SPADs). This is achieved using a new SPAD structure with integrated resistor and capacitor. NMOS-only pixel electronics are used to improve fill factor and to implement an addressable array of SPADs that are isolated from the array and column load. A 1T DRAM in each pixel is implemented to inhibit the output of high dark count rate (DCR) SPADs. The SiPM also achieves: a median DCR of ≈200Hz at 1.2V excess bias; low after pulsing; and a SPAD timing jitter of ≈95ps at 654nm with a column delay of ≈100-200ps.
Keywords :
CMOS image sensors; DRAM chips; MOSFET; avalanche diodes; photomultipliers; silicon; timing jitter; CMOS imaging technology; DCR SPAD; DRAM; NMOS-only pixel electronics; SPAD structure; SPAD timing jitter; addressable array; dark count rate SPAD; detection efficiency; fill factor; integrated capacitor; integrated resistor; photon detection probability; silicon photomultiplier; single photon avalanche diodes; size 11.6 mum; size 130 nm; size 450 nm to 750 nm; size 8 mum; Arrays; CMOS integrated circuits; MOS devices; Photomultipliers; Photonics; Random access memory; Silicon;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-1707-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2012.6343377
