An integration approach for graphene double-gate transistors

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO₂ dielectrics, shallow trench isolation between devices and atomic layer deposited Al₂O₃ top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing and other graphene-based devices.