Title :
Raising the Level of Abstraction for the Timing Verification of System-on-Chips
Author :
Chakraborty, Rupsa ; Chowdhury, Dipanwita Roy
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur
Abstract :
This paper proposes a general system-level timing verification method for System-on-Chips (SoC). Experiments have been carried out on several synthetic benchmark SoCs. Delays at the various interconnects are extracted from the SDF file generated after place and route. A graph of interconnects and cores is generated for each SoC, with the extracted delays back annotated as weights. Algorithms have been presented that verifies the timing criteria at various check points in the circuit.
Keywords :
formal verification; system-on-chip; timing; SDF file; SoC; system-level timing verification method; system-on-chip; timing criteria; Circuit analysis; Circuit synthesis; Clocks; Computer Society; Computer science; Delay estimation; Integrated circuit interconnections; System-on-a-chip; Timing; Very large scale integration; system-on-chip; timing verification;
Conference_Titel :
Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Conference_Location :
Montpellier
Print_ISBN :
978-0-7695-3291-2
Electronic_ISBN :
978-0-7695-3170-0
DOI :
10.1109/ISVLSI.2008.68
