DocumentCode
2013397
Title
Design of Fractal Image Compression on SOC
Author
Jedidi, A. ; Rejeb, B. ; Abid, M.
Author_Institution
Nat. Sch. of Eng., Univ. of Sfax, Sfax
fYear
2008
fDate
7-9 April 2008
Firstpage
479
Lastpage
482
Abstract
The technological revolution during the last years has carried out a great evolution especially in the multimedia domain. Nowadays, almost everyone benefits from various video applications such as TV broadcasting and video conferencing. This progress involves particularly an increase in the capacity of digital data transmission. As a result, data compression became increasingly significant for storage and transmission. In this paper, we present an algorithm for fractal image compression based on SOC in real time. The algorithm consists of a hardware and software part. The hardware part supports an expensive calculation; therefore it is conceived on RTL level. The coding algorithm was implemented on the Altera chart STRATIX-I. The functional blocks were implemented with clock rate of 410 MHz with a maximum flow data input of 13.2 Gbit/s.
Keywords
data compression; digital signal processing chips; fractals; hardware-software codesign; image coding; system-on-chip; SOC; TV broadcasting; data compression; digital data transmission; encoding algorithm; fractal image compression; hardware software design; video applications; video conferencing; Clocks; Data communication; Data compression; Fractals; Hardware; Image coding; Software algorithms; TV broadcasting; Video compression; Videoconference; FPGA; Fractal image compression; Functional simulation; RTL level design; Real time; SOC; Temporal simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Conference_Location
Montpellier
Print_ISBN
978-0-7695-3291-2
Electronic_ISBN
978-0-7695-3170-0
Type
conf
DOI
10.1109/ISVLSI.2008.26
Filename
4556845
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