Title :
At-speed testing of delay faults for Motorola´s MPC7400, a PowerPC TM microprocessor
Author :
Tendolkar, Nandu ; Molyneaux, Robert ; Pyron, Carol ; Raina, Rajesh
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
In this paper we present the novel built-in delay fault test concepts incorporated into Motorola´s MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit for issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower
Keywords :
automatic test pattern generation; boundary scan testing; delays; fault diagnosis; integrated circuit testing; microprocessor chips; 540 MHz; 63 MHz; Motorola MPC7400; PowerPC microprocessor; at-speed testing; delay faults; path delay fault test patterns; programmable clock control circuit; scan based testing; tester speed; transition fault test patterns; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Clocks; Delay; Logic testing; Microprocessors; Phase locked loops; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843819
