A unified VLSI architecture for decomposition and synthesis of discrete wavelet transform

Author

Sheu, Ming-hwa ; Shieh, Ming-Der ; Cheng, Shun-Fa

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Inst. of Technol., Taiwan, China

Volume

1

fYear

1996

fDate

18-21 Aug 1996

Firstpage

113

Abstract

This paper presents a unified VLSI architecture that can perform either Discrete Wavelet Transform (DWT) or inverse DWT (IDWT). Based on the Distributed Arithmetic method, an elementary computing module is designed, and used to construct the unified architecture. This architecture has the characteristics of no multiplier, lower hardware cost, shorter latency, higher throughput rate, and regular structure for VLSI implementation. Finally,the architecture is implemented into a single chip based on 0.8 μm CMOS technology. The chip area is 5100*5900 μm²

Keywords

CMOS digital integrated circuits; VLSI; digital arithmetic; digital signal processing chips; integrated circuit design; transforms; wavelet transforms; 0.8 micron; 5100 micron; 5900 micron; CMOS technology; chip area; discrete wavelet transform; distributed arithmetic method; hardware cost; inverse DWT; latency; regular structure; throughput rate; unified VLSI architecture; Arithmetic; CMOS technology; Computer architecture; Costs; Delay; Discrete wavelet transforms; Distributed computing; Hardware; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.594050

Filename

594050