DocumentCode :
2013598
Title :
Static compaction techniques to control scan vector power dissipation
Author :
Sankaralingam, Ranganathan ; Oruganti, Rama Rao ; Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear :
2000
fDate :
2000
Firstpage :
35
Lastpage :
40
Abstract :
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan vectors greatly increases the power dissipation for the vectors (generally the power becomes several times greater). The compacted scan vectors often can exceed the power constraints and hence cannot be used. It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced. A static compaction procedure is presented that can be used to find a minimal set of scan vectors that satisfies constraints on both average power and peak power. The proposed approach is simple yet effective and can be easily implemented in the conventional test vector generation flow used in industry today
Keywords :
automatic test pattern generation; boundary scan testing; flip-flops; integrated circuit testing; logic testing; average power dissipation; current spikes; final test set; heat dissipation; scan vector power dissipation; static compaction techniques; switching activity; test cubes; test vector generation flow; Circuit testing; Clocks; Compaction; Costs; Flip-flops; Packaging; Power dissipation; Power supplies; Switches; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
ISSN :
1093-0167
Print_ISBN :
0-7695-0613-5
Type :
conf
DOI :
10.1109/VTEST.2000.843824
Filename :
843824
Link To Document :
بازگشت