Title :
Critical gate module process enabling the implementation of a 50A/600V AlGaN/GaN MOS-HEMT
Author :
Khalil, S.G. ; Chu, R. ; Li, R. ; Wong, D. ; Newell, S. ; Chen, X. ; Chen, M. ; Zehnder, D. ; Kim, S. ; Corrion, A. ; Hughes, B. ; Boutros, K. ; Namuduri, C.
Author_Institution :
HRL Labs., LLC, Malibu, CA, USA
Abstract :
Two critical processes within the gate module of GaN-based MOS-HEMT with significant impact on device robustness and performance were identified and are presented in this paper. Specifically, data highlighting the impact of the number of cycles of the atomic layer etching of the AlGaN barrier to recess the gate region and the sequence of the gate dielectric anneal step on device performance are discussed. The optimization of these two critical steps enabled the implementation of a 50A/600V with an off-state leakage current of 455 μA at 600V and on-state resistance of 41mΩ at VGS=2.5V.
Keywords :
III-V semiconductors; aluminium compounds; annealing; atomic layer deposition; circuit optimisation; dielectric devices; electric resistance; etching; gallium compounds; high electron mobility transistors; leakage currents; wide band gap semiconductors; AlGaN-GaN; MOS-HEMT; atomic layer etching; critical gate module process; current 455 muA; current 50 A; device performance; device robustness; gate dielectric anneal sequence; gate region; off-state leakage current; on-state resistance; optimization; voltage 600 V; Aluminum gallium nitride; Aluminum oxide; Dielectrics; Leakage current; Logic gates; Performance evaluation;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-1707-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2012.6343395
