• DocumentCode
    2013745
  • Title

    A framework to minimize test escape and yield loss during IDDQ testing: a case study

  • Author

    Cheung, Hugo ; Gupta, Sandeep K.

  • Author_Institution
    Burr-Brown Corp., Tucson, AZ, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    89
  • Lastpage
    96
  • Abstract
    We describe a new framework to minimize test escape (TE) and yield loss (YL) during IDDQ testing. The proposed framework defines the concept of critical severity of a fault Sk´, that provides a link between the fault magnitude and violation of one or more specifications. The framework provides various strategies to select the values of IDDQ threshold and provides a mechanism to compute test escape and/or yield loss. The framework is illustrated using an SRAM as a case study. The results demonstrate various trade-offs that can be explored using the framework
  • Keywords
    CMOS memory circuits; SRAM chips; VLSI; fault diagnosis; integrated circuit testing; integrated circuit yield; CMOS; IDDQ testing; SRAM; critical severity; fault magnitude; test escape; yield loss; Circuit faults; Circuit testing; Computer aided software engineering; Identity-based encryption; Logic devices; Logic testing; Reactive power; Switches; System testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2000. Proceedings. 18th IEEE
  • Conference_Location
    Montreal, Que.
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-0613-5
  • Type

    conf

  • DOI
    10.1109/VTEST.2000.843831
  • Filename
    843831
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2013745