Test and debug of networking SoCs-a case study

Author

Bommireddy, A. ; Khare, J. ; Shaikh, S. ; Su, S.-T.

Author_Institution

Level One Commun., Santa Clara, CA, USA

fYear

2000

fDate

2000

Firstpage

121

Lastpage

126

Abstract

This paper describes the test challenges faced and testability features implemented on Level One´s networking System on Chip (SoC), IXE2000. The IXE2000 SoC is a 20+ million transistor Layer 2/3/4 Switch with 24 10/100 Mbps and 2 1000 Mbps Ethernet ports, and a predominantly IP-based design. The chip had constraints in terms of both design time and total system costs, which added an extra burden on test. The paper discusses how these constraints led to the current testability solutions and debug features on the chip

Keywords

application specific integrated circuits; automatic testing; built-in self test; design for testability; integrated circuit testing; local area networks; logic testing; 10 to 1000 Mbit/s; Ethernet ports; IP-based design; IXE2000; Layer 2/3/4 Switch; Level One; debug features; design time; networking SoCs; testability features; testability solutions; total system costs; Business communication; Clocks; Computer aided software engineering; Costs; Design for manufacture; Ethernet networks; IP networks; Switches; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Conference_Location

Montreal, Que.

ISSN

1093-0167

Print_ISBN

0-7695-0613-5

Type

conf

DOI

10.1109/VTEST.2000.843835

Filename

843835