Design of Sequential Circuits in Multilayer QCA Structure

This work targets developing sequential circuits in QCA under multilayer framework. The main goal is to build an efficient methodology to achieve high device density as well as minimum delay in logic realization. This is the first attempt in its kind of design with active QCA multilayer. The synthesis of conventional SR, JK, D and T flip-flops is reported following the multilayer QCA technology. The characterization of flip-flops is done with achievement of 100% fault tolerance under any kind of additional cell deposition QCA defect. It is established that the proposed multilayer design achieves 77% improvement in device density simultaneously with 50% improvement in delay than that of the existing conventional design approaches. The proposed design further achieves the minimum clock zone (3-clock) desired for sequential logic in QCA technology.