Title :
Integrating logic BIST in VLSI designs with embedded memories
Author :
Chickermane, Vivek ; Richter, Scott ; Barnhart, Carl
Author_Institution :
Test Deisgn Autom., IBM Corp., Endicott, NY, USA
Abstract :
Logic BIST techniques normally focus on testing random logic blocks. If one observes the current design trends for high-performance ASICs, the number and size of embedded memories is increasing rapidly. This presents several challenges to the design and integration of at-speed logic BIST when the number of bits of embedded memories is a large percentage of the total number of storage bits in the design. This paper will discuss some novel techniques to address the DFT and clocking considerations in designs with extensive usage of embedded memories
Keywords :
VLSI; application specific integrated circuits; built-in self test; clocks; design for testability; integrated circuit testing; logic testing; DFT; VLSI designs; at-speed logic BIST; clocking considerations; embedded memories; high-performance ASICs; logic BIST; storage bits; Built-in self-test; Chromium; Circuit testing; Clocks; Logic design; Logic testing; Polynomials; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843840
