• DocumentCode
    2013997
  • Title

    A general BIST-amenable method of test generation for iterative logic arrays

  • Author

    Boateng, Kwame Osei ; Takahashi, Hiroshi ; Takamatsu, Yuzo

  • Author_Institution
    Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    171
  • Lastpage
    176
  • Abstract
    In this work, we call a set of a constant number of test patterns that have a fixed fault coverage for any size of a given ILA a fixed coverage fixed size test set (FixCoST). In this paper, we first show the existence of FixCoSTs, each test pattern of which is applied to the rows and columns of the array under test, as binary patterns that are repetitions of a few cell-input patterns. Such FixCoSTs can be applied in a BIST framework. Next, we devise a means and formulate measures to evaluate the individual repetitive test patterns of such a FixCoST and the FixCoST as a set. Then, we exploit the repetitive nature of the constituent test patterns of the FixCoSTs to develop a BIST-amenable method for generating FixCoSTs that apply all permutations of binary patterns to each cell of the ILA under test
  • Keywords
    automatic test pattern generation; built-in self test; cellular arrays; fault diagnosis; logic arrays; logic testing; BIST framework; BIST-amenable method; FixCoST; binary patterns; cell-input patterns; fixed coverage fixed size test set; fixed fault coverage; iterative logic arrays; test generation; test patterns; Iterative methods; Logic arrays; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2000. Proceedings. 18th IEEE
  • Conference_Location
    Montreal, Que.
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-0613-5
  • Type

    conf

  • DOI
    10.1109/VTEST.2000.843842
  • Filename
    843842