Title :
Path Delay Fault Test Set for Two-Rail Logic Circuits
Author :
Namba, Kazuteru ; Ito, Hideo
Author_Institution :
Grad. Sch. of Adv. Integration Sci., Chiba Univ., Chiba, Japan
Abstract :
Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword vector pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.
Keywords :
logic circuits; logic testing; over-testing; path delay fault test set; two-rail logic circuits; Circuit faults; Circuit testing; Combinational circuits; Delay; Electrical fault detection; Logic circuits; Logic testing; Robustness; System testing; Very large scale integration; monotone function; over-testing; path delay fault testing; testability; two-rail logic circuit;
Conference_Titel :
Dependable Computing, 2008. PRDC '08. 14th IEEE Pacific Rim International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-0-7695-3448-0
Electronic_ISBN :
978-0-7695-3448-0
DOI :
10.1109/PRDC.2008.8
