• DocumentCode
    2014284
  • Title

    Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms

  • Author

    Mishra, Goutam ; Yan Lin Aung ; Meiqing Wu ; Siew-Kei Lam ; Srikanthan, Thambipillai

  • Author_Institution
    Electron. & Commun. Eng., Indian Inst. of Inf. Technol. (Allahabad), Allahabad, India
  • fYear
    2013
  • fDate
    10-12 Dec. 2013
  • Firstpage
    98
  • Lastpage
    102
  • Abstract
    This paper describes motivation and hardware architecture for resizing input image frames from the camera in order to support real-time scale-invariant object recognition. Conventional implementation of object detection algorithms such as histogram of oriented gradients (HOG) based feature extraction, face detection using Haar classifiers often perform image resizing during the object recognition process. Our investigation reveals that this incurs significant performance overhead due to frequent memory accesses that are required for image resizing. This has motivated our approach to perform online resizing - simultaneously resizing of the input image when it is loaded into frame buffer memory - prior to the object recognition process. We propose a hardware architecture to accelerate image resizing and describe a hybrid processor-accelerator platform to generate different sizes of an image in real-time for object recognition.
  • Keywords
    cameras; computer architecture; image classification; image processing equipment; image reconstruction; object detection; object recognition; HOG based feature extraction; Haar classifiers; camera; face detection; frame buffer memory; hardware architecture; histogram of oriented gradients based feature extraction; hybrid processor-accelerator platform; object detection algorithms; object recognition process; online resizing; real-time image resizing hardware accelerator; real-time scale-invariant object recognition; Algorithm design and analysis; Computer architecture; Feature extraction; Field programmable gate arrays; Hardware; Object detection; Real-time systems; FPGA; HOG feature; Haar classifier; Image processing; Image resize;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic System Design (ISED), 2013 International Symposium on
  • Conference_Location
    Singapore
  • Print_ISBN
    978-0-7695-5143-2
  • Type

    conf

  • DOI
    10.1109/ISED.2013.26
  • Filename
    6808649