Testing, verification, and diagnosis in the presence of unknowns

Author

Jain, A. ; Boppana, V. ; Mukherjee, R. ; Jain, J. ; Fujita, M. ; Hsiao, M.

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2000

fDate

2000

Firstpage

263

Lastpage

269

Abstract

Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs are important problems in industry. In this paper we address these problems when portions of the design may be unspecified. Two approaches to solve these problems have been presented: (1) solving Boolean satisfiability under unknown constraints, and (2) a network modification-based solution. Experimental results on constrained equivalence checking, enhancement of error diagnosis resolution for combinational circuits, and ATPG for IP-based designs have been presented on the ISCAS 85 benchmark and industrial circuits

Keywords

Boolean functions; automatic test pattern generation; combinational circuits; fault diagnosis; industrial property; integrated circuit testing; ATPG; Boolean satisfiability; IP-based designs; ISCAS 85 benchmark circuits; combinational circuits; constrained equivalence checking; error diagnosis resolution; fault diagnosis; industrial circuits; network modification-based solution; unknown constraints; unspecified design portions; Algorithm design and analysis; Circuit analysis; Combinational circuits; Costs; Electronic switching systems; Error correction; Fault diagnosis; Process design; Testing; Tires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Conference_Location

Montreal, Que.

ISSN

1093-0167

Print_ISBN

0-7695-0613-5

Type

conf

DOI

10.1109/VTEST.2000.843854

Filename

843854