DocumentCode
2014391
Title
Trench Isolation Technology for 0.35/spl mu/m Device by Bias ECR CVD
Author
Gocho, T. ; Morita, Y. ; Sato, J.
Author_Institution
Process Technology Dept., UlSI R&D Group, Sony Corp., Japan
fYear
1991
fDate
28-30 May 1991
Firstpage
87
Lastpage
88
Keywords
Buffer layers; Diodes; Etching; Fluid flow; Isolation technology; Leakage current; Planarization; Protection; Research and development; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on
Conference_Location
Oiso, Japan
Type
conf
DOI
10.1109/VLSIT.1991.706003
Filename
706003
Link To Document