Detection of inter-port faults in multi-port static RAMs

Author

Zhao, J. ; Irrinki, S. ; Puri, M. ; Lombardi, F.

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA

fYear

2000

fDate

2000

Firstpage

297

Lastpage

302

Abstract

This paper deals with testing of inter-port faults in multi-port static random access memories (SRAMs). An inter-port fault is caused by a short between word/bit lines of different ports in a multi-port SRAM. By considering different implementations of the SRAM and its layout, an approach with achieves 100% coverage of fault detection, is proposed. The two-step approach is based on two novel algorithms: MMCA (Modified March C Algorithm) and WIPD (Write Inter-Port Detection). It is shown that inter-port fault detection is a combinatorial problem; hence, MMCA and WIPD must be executed a multiple number of times depending on the types, number of ports and line arrangement in the layout

Keywords

SRAM chips; automatic testing; fault diagnosis; integrated circuit testing; multiport networks; MMCA; WIPD; combinatorial problem; fault detection; inter-port faults; line arrangement; modified March C algorithm; multi-port static RAMs; two-step approach; word/bit lines; write inter-port detection; Computer science; Electrical fault detection; Fault detection; Large scale integration; Logic; Random access memory; Read-write memory; SRAM chips; Semiconductor device manufacture; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Conference_Location

Montreal, Que.

ISSN

1093-0167

Print_ISBN

0-7695-0613-5

Type

conf

DOI

10.1109/VTEST.2000.843858

Filename

843858