Title :
Detectability conditions for interconnection open defects
Author :
Champac, Victor H. ; Zenteno, Antonio
Author_Institution :
Dept. of Electron. Eng., INAOE, Puebla, Mexico
Abstract :
The detectability of interconnection opens by logic and IDDQ testing is investigated. Opens in interconnection paths disconnect the driven gate(s) from the driving gate. An electrical model for interconnection opens is used to predict the detectability of this type of open. Using the proposed model, explicit analytical expressions have been obtained to determine the conditions for reliable detection of this defect by logic and IDDQ testing. The cases of full controllability and non-full controllability of the signals at the coupling lines have been analysed. The effect of the trapped charge during fabrication has also been investigated. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. The detectability dependency of interconnection opens on the test generation process has been analyzed
Keywords :
CMOS digital integrated circuits; automatic testing; integrated circuit interconnections; integrated circuit testing; logic testing; IDDQ testing; coupling lines; detectability conditions; detectability dependency; electrical model; full controllability; interconnection open defects; interconnection paths; logic testing; reliable detection; test generation process; Astrophysics; Circuit testing; Controllability; Fabrication; Frequency; Integrated circuit interconnections; Logic testing; Optical interconnections; Predictive models; Voltage;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843859
